How the data loads in cache?

[RyoDC]

I mean, we have a data cache, for example, about of 16 Kbytes on SH4 processor.
How the processor knows which data and when (and how much of them) to load into cache?

[nymus]

This is a pretty good explanation.

[TapamN]

The SH4 loads data into the cache when the program tries to access cacheable memory and the data isn't already in the cache. Main RAM is usually accessed as cacheable, while hardware is usually accessed as uncacheable. When the SH4 load stuff into cache, it always loads a block of 32 bytes. The start of that block is the address of the memory access rounded down to a multiple of 32. So if the address accessed is between 0-31, the block loaded will contain the data from 0-31; if the address is between 32-63, the block loaded will contain the data from 32-63; etc.

[RyoDC]

So there will be some delay, right? Is there's any way to pre-load that data?

What data are initially in the cache?

[Ayla]

You can use GCC's __builtin_prefetch for that purpose.

[BlueCrab]

You can use GCC's __builtin_prefetch for that purpose.

Or, of course, just use the pref instruction in assembly.

[GyroVorbis]

So there will be some delay, right? Is there's any way to pre-load that data?

What data are initially in the cache?

Yeah, there's considerable delay for a cache miss. That's why cache optimization is so important for time-critical algorithms.

Or, of course, just use the pref instruction in assembly.

Code: Select all

#define PREFETCH(addr) __asm__ __volatile__("pref @%0" : : "r" (addr));