I have a question, coming from SH2.
The SH2 Programming Manual states (§7.4.3, p174) :
That means :When an instruction is located in on-chip memory (ROM/RAM) or on-chip cache, there are instruction fetch stages (‘if’ written in lower case) that do not generate bus cycles as explained in section 7.4.2 above. When an "if" is in contention with an MA, the slot will not split, as it does when an IF and an MA are in contention, because "if"s and MAs can be executed simultaneously. Such slots execute in the number of states the MA requires for memory access, as illustrated in figure 7.8.
When programming, avoid contention of MA and IF whenever possible and pair MAs with ifs to increase the instruction execution speed
Code: Select all
.align 4
MOV.L @R2,R3 IF ID EX MA WB
ADD R0,R1 if ID EX
MOV R4,R5 IF ID EX
SHLR R6 if ID
But if I have :
Code: Select all
.align 4
NOP IF ID EX
MOV.L @R2,R3 if ID EX MA WB
ADD R0,R1 IF ID EX
MOV R4,R5 if ID EX
SHLR R6 - IF ID
NB: I'm purposedly letting the superscalar thing aside here.
I didn't find anything about the subject in the Hitachi manuals, especially Programming Manual, figure 8.3 p166
The instructions bus seems to be 32-bits wide, so would allow two instructions at a time.
So here is my question : does SH4 have the same contention problem as SH2, or did the smart engineers from Hitachi manage to get around it?