SH4 Interrupt handling

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Insane DCEmu
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SH4 Interrupt handling

Post by Newbie » Wed Sep 07, 2016 1:36 pm

Hi everybody,

In X86 architecture, INT instruction is used to generate a software interrupt.
The interrupt number is formatted as a byte value.

When written in assembly language, the instruction is written like this:
INT X.

In real mode :
the X86 processor calls one of the 256 functions pointed to by the interrupt address table, which is located in
the first 1024 bytes of memory.

For example, the INT 3 instruction is defined for use by debuggers to temporarily replace an instruction in a
running program in order to set a breakpoint.

The same way, bit number 8 of the EFLAGS register is the trap flag.
When set, a single step exception is generated.
I found in KOS source code a very interesting piece of code name gdb_stub.c.

Reading the code, I imagine that there are non "specialized" software interrupt to make software breakpoints and
single stepping like INT 3, EFLAGS in x86.

This code used a generic TRAPA instruction with a 0xFF code ( asm("trapa #0xff"::) ).
I imagine again that any code could make the same desired effect.

Am i right ?

The next question is about how development hardware handle debugging, as I do not own such hardware
I ask myself several times how the code is break (by software not hardware) and single stepped.

Is those machines used TRAPPA instructions (like in gdb_stub.c source code) ?

Is KOS using internally some TRAPPA features or is it free to make own handler for whatever TRAPPA code (0-255)
without crashing something ?

To finish, I would write my own handler for TRAPA software interruption.
In KOS there is a function to make it easily named "irq_handle_trapa" :

Code: Select all

/** \brief  Set or remove a handler for a trapa code.
    \param  code            The value passed to the trapa opcode.
    \param  hnd             A pointer to the procedure to handle the trap.
    \retval 0               On success.
    \retval -1              If the code is invalid (greater than 0xFF).
*/
int trapa_set_handler(irq_t code, irq_handler hnd); 
But as I want to learn more about SH4 Assembly, could anybody help me figure out how it could be done in pure assembly ?

Thanks a lot for your help.
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Re: SH4 Interrupt handling

Post by bogglez » Wed Sep 07, 2016 1:42 pm

Either read the documentation for the SH4 by renesas, or look at the irq*c files and grep for irq in the few assembly. s files.
I also made a topic about interrupt handling on this forum before, where you can read about my learning process.
The processor also has a debugging mode which seems to allow single stepping etc but I haven't used it
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Re: SH4 Interrupt handling

Post by Newbie » Wed Sep 07, 2016 4:27 pm

The processor also has a debugging mode which seems to allow single stepping etc but I haven't used it
I am not interesting on hardware irq only software ones.
Either read the documentation for the SH4 by renesas, or look at the irq*c files and grep for irq in the few assembly. s files.
I have read both software and hardware manuals but there are not sample with comments to explain a basic handler.

If you have a link to a bunch of .s samples : you're welcome.
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Re: SH4 Interrupt handling

Post by bogglez » Wed Sep 07, 2016 4:52 pm

I posted using my phone earlier, so I was unable to post examples.

I think you want to look at kos/kernel/arch/dreamcast/kernel/entry.s
But it's not implemented in pure assembly, it's mixed with C.

I did the same in pure assembly (but the handler that's called is a C function, you can replace it with assembly instead of jumping of course).

viewtopic.php?f=29&t=104038

I'll attach some code from a project of mine. Read start.s and pay attention to the vma_table especially. Check the other two C files to see what functions are called (ignore the other stuff).
My code is probably more readable than the KOS code so it should give you a good idea.
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Re: SH4 Interrupt handling

Post by Newbie » Fri Sep 09, 2016 6:22 am

Thanks a lot.
It is very useful!
Now things are clear :)
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