I found in KOS source code a very interesting piece of code name gdb_stub.c.
In X86 architecture, INT instruction is used to generate a software interrupt.
The interrupt number is formatted as a byte value.
When written in assembly language, the instruction is written like this:
In real mode :
the X86 processor calls one of the 256 functions pointed to by the interrupt address table, which is located in
the first 1024 bytes of memory.
For example, the INT 3 instruction is defined for use by debuggers to temporarily replace an instruction in a
running program in order to set a breakpoint.
The same way, bit number 8 of the EFLAGS register is the trap flag.
When set, a single step exception is generated.
Reading the code, I imagine that there are non "specialized" software interrupt to make software breakpoints and
single stepping like INT 3, EFLAGS in x86.
This code used a generic TRAPA instruction with a 0xFF code ( asm("trapa #0xff"::) ).
I imagine again that any code could make the same desired effect.
Am i right ?
The next question is about how development hardware handle debugging, as I do not own such hardware
I ask myself several times how the code is break (by software not hardware) and single stepped.
Is those machines used TRAPPA instructions (like in gdb_stub.c source code) ?
Is KOS using internally some TRAPPA features or is it free to make own handler for whatever TRAPPA code (0-255)
without crashing something ?
To finish, I would write my own handler for TRAPA software interruption.
In KOS there is a function to make it easily named "irq_handle_trapa" :
Code: Select all
/** \brief Set or remove a handler for a trapa code. \param code The value passed to the trapa opcode. \param hnd A pointer to the procedure to handle the trap. \retval 0 On success. \retval -1 If the code is invalid (greater than 0xFF). */ int trapa_set_handler(irq_t code, irq_handler hnd);
Thanks a lot for your help.