Thank you again @TapamN for you quick and complete answer ^^

TapamN wrote: ↑Fri Jul 30, 2021 2:07 am If two instructions can't be executed in parallel, it runs the first instruction this cycle, then the next cycle it tries to run the second and third instructions in parallel.

OK, now I get it. Thank you very much for your answer ^^

Totally makes sense. Thank you so much for the answer and the reminder about the Harvard / Von Neumann architecture ˆˆ

Add: If we use the C code given by @nymus in the "SH4 assembly function call in C" : int test(int values[5]) { int total = 0; for(int i = 0; i < 5; ++i) { total += values[i]; } return total; } The -O3 compiled code is: _test: mov.l @(4,r4),r1 I D X M S mov.l @r4,r0 i D X M S add r1,r0 I D ...

Hello to all. I have a question, coming from SH2. The SH2 Programming Manual states (§7.4.3, p174) : When an instruction is located in on-chip memory (ROM/RAM) or on-chip cache, there are instruction fetch stages (‘if’ written in lower case) that do not generate bus cycles as explained in section 7....

Hello to you all, this is my first post here ^^ I've done my share of coding on Genesis and 32X, and am now getting into Dreamcast (I love Hitachi SuperH!). As you know, one of the main differences between SH2 and SH4 is the latter being superscalar. This means that, for certain instructions, two ca...